Method and apparatus for dynamically interfacing with a plurality of peripheral ports

ABSTRACT

A method of dynamically interfacing an application processor with a plurality of peripheral ports is shown, including the use of an expanded memory interface for controlling a plurality of memory components for an application processor external to the interface. The application processor is connected to the expanded memory interface, which is in turn coupled to at least one status port to facilitate communication between the application processor and the status port.

This a continuation of application Ser. No. 08/196,046 filed Feb. 14,1994, now abandoned, which is a continuation of Ser. No. 07/424,853,filed Oct. 20, 1989, now U.S. Pat. No. 5,317,707.

FIELD OF THE INVENTION

The present invention relates generally to microprocessors andmicrocomputers, and specifically to an expanded memory interface forapplication microprocessors and microcomputers.

BACKGROUND OF THE INVENTION

The terms microprocessor and microcomputer often are usedinterchangeably even though a microprocessor technically does not haveany memory on the same chip with the processor. A microcomputer, on theother hand, includes a processor and at least some memory on the samechip. Since the present invention can be utilized with bothmicroprocessors and microcomputers the terms will be usedinterchangeably herein. It is to be understood, however that use of oneterm includes the other unless the context indicates otherwise.

Microprocessors running application program, such as DOS based programs,have the ability to directly address only a limited amount ofconventional memory. In the case of DOS based application processorsthat limit is 1 megabyte (MB) of memory. This limit of memory can beexpanded by using an Expanded Memory System (EMS). Such an EMS isdisclosed in the "AST-Enhanced Expanded Memory Specification (EEMS)Technical Reference Manual", 000408-001 A. September, 1986. A similarEMS is disclosed in "The MS-DOS Encyclopedia", Microsoft Press, Redmond,Wash., 1988. Duncan, Ray General Editor.

In general an EMS is provided by mapping 16 KB pages of expanded memoryinto a 64 KB area called the page frame, above the 640 KB memoryboundary within the conventional memory. The DOS kernel does not takepart in expanded memory manipulations and does not use expanded memoryfor its own purposes. The manipulation and management of the expandedmemory is performed by an EMS controller. Typically, however, EMS memoryis usually conceived as a fixed mass of RAM permanently attached to theDOS processor and controlled by a discrete realization of the EMScontroller.

Extended memory (EXT) is that memory storage at addresses above 1 MBthat can be accessed directly by a microprocessor running in protectedmode. Protected mode operating systems, such as XENIX and OS/2, can useextended memory for execution of programs. DOS based applicationprograms, on the other hand, run in real mode, and ordinarily cannotexecute from extended memory or even address that memory for storage ofdata. Some microprocessors can theoretically have as much as 15 MB ofextended memory installed in addition to the usual 1 MB of conventionalmemory address space.

Microprocessors can support three different types of memory.Conventional memory is the term used for the 1 MB of linear addressspace that can be accessed by the microprocessor running in real mode.Expanded memory (EXP) can be made available by mapping 16 KB pages intoa 64 KB space within the 1 MB of conventional memory. Extended memory(EXT) relates to that memory above 1 MB that can be directly accessed bya microprocessor running in protected mode. The memory media can, ofcourse, include a wide variety of structures, such as ROM, RAM, floppydisks, hard disks and others.

SUMMARY OF THE INVENTION

It is one object of the present invention to provide an expanded memoryinterface which can be used with a variety of microprocessors in avariety of applications.

It is another object of the present invention to provide an expandedmemory interface that can be used in applications requiring small size,low power and removable media such as a laptop computer.

It is another object of the present invention to provide a memoryinterface which can be used to support conventional, expanded andextended memory in a variety of media.

It is another object of the present invention to provide an expandedmemory interface which can support both fixed and removable memorymedia.

It is another object of the present invention to provide a expandedmemory interface in which the various memory media are treated as fIoppydisks by the application processor.

Another object of the present invention is to provide an expanded memoryinterface which allows the application processor to be controlled by anexit processor for power conservation.

It is another object of the present invention to provide an expandedmemory interface in which an application processor is connected to anexternal processor via status ports.

It is another object of the present invention to provide an expandedmemory interface by which the application processor is controlled by anexternal processor via an interrupt of the application processor.

It is another object of the present invention to provide a generalizedcommunication interface between an application processor and an externalprocessor to allow direct communication between the processors.

The expanded memory interface of the present invention includes anexpanded memory controller capable of addressing up to 32 MB of RAM. TheEMS address is contained in four registers each of which has twelvebits. Eleven of the bits are the high order address bits for the EMSaddress which together with the first 14 bits of the conventional memoryprovide the 25 bits required to address 32 MB of memory. The 12th bit ineach register is an enable bit.

The 32 MB of EMS memory are divided into two 16 MB blocks. The first 16MB block is provided to be occupied by expanded memory which increasesthe usable memory space of the processor. The first 16 MB block isprovided to be occupied by eight defined "Card Slots" which may beeither ROM or RAM in a variety of media suitable to the particularsituation. Each "Card Slot" is coupled to a status port which contains aplurality of status change bits used to indicate the status of the "CardSlot" to the application microprocessor via the expanded memorycontroller. The card slots are monitored by another processor to providestatus information to the application processor. The expanded memoryinterface and the status ports are transparent to the applicationprocessor.

Other objects and advantages may become apparent to those skilled in theart upon a reading of the following disclosure with reference to theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partially schematic and partially block diagram of amicrocomputer using the expanded memory interface according to thepresent invention;

FIG. 2 is a block diagram of an expanded memory controller of thepresent invention used in the microcomputer of FIG. 1; and

FIG. 3 is a block diagram of the status ports of the present inventionused in the microcomputer of FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will be discussed herein in connection with themicrocomputer shown in FIG. 1. It is to be understood however, that thepresent invention can be used in a variety of devices, including withoutlimitation, application specific microprocessors, printers and otherproducts using microprocessors needing extended or expanded memory.

Referring now to the microcomputer 10 shown in FIG. 1, an applicationprocessor 12, such as the 80286 processor shown, has a real time clockand NVRAM 13, programmable read only memory 14, dynamic random accessmemory 15, memory control and address buffers 16, data buffers 17, clockcontrol 18 and parallel and serial ports 19 connected in a typical andknown fashion. It is to be noted that while a DOS based microprocessor80286 is shown, the present invention can be utilized with anyapplication processor.

The main PC Board 22 of the microcomputer 10 contains the externalmicroprocessor 38, the expanded memory interface 31 and a variety ofperipherals as shown. Static RAM 23 is coupled with the address bus 20for communication with the application processor 12. Character sets arestored in ROM 24 and coupled to the LCD 26 (off board) via CGA displaycontrol 25 for outputting information to the display 26.

The embodiment shown also has a poppy disk interface 27 connected fordata communication between data bus 21, address bus 20 and floppy disk28. A hard disk interface 29 is provided for data communication with ahard disk drive 30.

The expanded memory interface including the status ports are shown ingreater detail in FIGS. 2 and 3 respectively. The expanded memoryinterface is resident in the expanded memory specification applicationspecific integrated circuit EMSASIC 31, and will be discussed in furtherdetail hereinafter. Coupled to the EMSASIC 31 are ROM 32, RAM 37, cardslots 33, programmable static RAM 34 and external processor 38 whichcontrols the expanded extended memory operations. The term "card slot"is used herein in the broad sense of any type of memory. Accordingly,RAM 32 and ROM 37 can be considered card slots.

Connected to the external microprocessor 38 is modem 39, which is alsoconnected directly to data bus 21 and address bus 20 for communicatingdirectly with the application microprocessor 12. Keyboard control 40 isconnected to external microprocessor 38 for controlling user access tothe microcomputer 10 via keyboard 41. RS232 interface 42 is alsoprovided for connecting the parallel and serial ports 19 to anasynchronous port (not shown).

As previously stated, EMSASIC 31 contains the EMS controller 50 of FIG.2. The EMS controller includes a 4×12 bit page register 51 for mappingthe expanded memory into four 16 KB pages of the conventional memory ofthe application processor 12. The page register 51 receives data signalsfrom the data bus 21 of the application processor 12 and outputs an EMSaddress in accordance with the output of I/O decoder 52. I/O decoder 52receives address signals from the address bus 20 of the applicationprocessor 12 as well as an I/O read/write signal.

The address from the application processor address bus 20 is alsoreceived by the window decode register 53 together with a memoryread/write signal to select one of the 4×12 bit registers in pageregister 51 via select register 54. A slot decode 56 is provided toenable the selected card slots 33. Register readback MUX 55 is alsoprovided for multiplexing between slot decoder 56 and applicationprocessor data bus 21.

FIG. 3 shows the status ports 60 resident in the EVMASIC 31 which linkthe application processor 12 and the external processor 38. The statusports 60 include a plurality of registers which can be defined toprovide a generalized communication interface between the applicationprocessor 12 and the external processor 38. The particular ports shownin FIG. 3 will now be discussed, it being understood that theconfiguration and function of the various ports can be changed orenhanced to meet the needs of a particular application without departingfrom the spirit and scope of the present invention.

The status port configuration shown allows the external processor 38 tomonitor the card slots 33 and alert the application processor 12 to anychange in status at the card slot. This is accomplished by the externalprocessor 38 setting a bit in the NMI status port 61 and then togglingthe non-maskable interrupt of the application processor. The applicationprocessor 12 then checks the N status port 61 to determine what generalstatus change has occurred and accesses individual status pots 67,73 tolocate the specific change in status that has occurred. After takingappropriate response steps to the change in status, the applicationprocessor 12 clears the NMI status port 61 which signals the externalprocessor 38 that the status change has been recognized and serviced bythe application processor 12.

The NMI status port 61 shown has 6 bits defined as follows:

    ______________________________________                                        Bit Number                                                                            Name          Definition                                              ______________________________________                                        0       POWER LOW     When set, signals the application                                             processor that the application                                                click speed should be reduced.                          1       CRADLE CHANGE When set, signals the application                                             processor that the peripheral                                                 cradle has either been connected                                              or disconnected                                         2       CARD CHANGE   When set, signals the application                                             processor that a memory card has                                              either been inserted or removed                         3       BATTERY STATUS                                                                              When set, signals the application                               CHANGE        processor that the battery of one                                             of the removable battery cards                                                has gone low                                            4       COPROCESSOR   When set, signals the application                               DISABLE       processor to disable the                                                      coprocessor                                             5       DISPLAY READY When set, signals the application                                             processor that the LCD display is                                             ready to accept data                                    ______________________________________                                    

A second status pot contained in the interface 60 is the jumper port 66which provides configuration information to the application processor12. Jumper port 66 is an 8 bit register that can be set manually viajumper switches. In the embodiment shown, the bits in the jumper port 66are defined as follows:

    ______________________________________                                        Bits 0-3   Define the I/O port address of the EMS address                                registers                                                          Bit 4      Cradle Status Bit- When low, the cradle is                                    attached: When high, it is disconnected                            Bits 5-7   Define the type of LCD being used                                  ______________________________________                                    

The present embodiment can utilize battery powered removable memorycards to be stored in some of the card slots 33. Expanded memoryinterface 66 also has a card battery status port 67 comprising thebattery status read buffer 68 and the battery status latch 69. The cardbattery status port 67 is defined to contain the status of the batteryof each card slot 33. The card battery status port 67 has eight bits.One bit is utilized for each card slot. When the bit is high, thebattery for the memory card in that slot is good. When the bit is low,the battery in the memory card in that slot is bad.

The engine status port 70 is an 8 bit write only port with its bitsdefined as follows:

    ______________________________________                                        Bit 0  STC         Written by BIOS to indicate the power                                         on self test (POST) is complete bit                                           is low during POST and high when                                              complete                                                   Bit 1  VID DISABLE Written during POST indicating that                                           video adapter should be disabled                           Bits 4-7                                                                             EMS BASE    Written by the BIOS during POST to in-                            ADDRESS     dictate the starting adress of the EMS                                        window                                                     ______________________________________                                    

The eight card status ports 73 each correspond to one of the card slots.Each is an eight bit register having the following bit definitions:

    ______________________________________                                        Bits 0-1   Indicates whether the memory card battery for                                 that slot is good, low or not present                              Bit 2      When high, indicates the presence of a card in                                the slot                                                           Bit 3      When high, indicates that the card cannot be                                  written                                                            Bit 7      When high, indicates that the current NMI                                     interupts resulted from a status change in this                               card                                                               ______________________________________                                    

In operation, the EMS controller 50 of FIG. 1 functions as follows.During power up, the BIOS of the application processor 12 locates anunused 64 KB "hole" in the 1 MB conventional memory of the applicationprocessor 12. The starting address of this "hole" becomes the "baseaddress" of the EMS window and this address is written to the enginestatus port 70 at bits 4-7 of that port. The EMS window is divided intofour 16 KB pages. Each page is physically represented by one of the 4×12registers 51 which contain th effective EMS memory address. An EMSsoftware driver continuously updates the page address registers 51 sothat the application processor 12 "sees" the effect of a largecontinuous memory space.

The external microprocessor 38 monitors the various memory componentsand signals the application processor 12 when changes occur via thestatus ports 61, 67, 73 by writing bit changes to the register in thestatus ports. The application processor 12 is notified of any changes instatus via the port 61. If, for example, a removable memory card (notshown) is inserted into card slot 4 (not shown), bit 2 of the statusport associated with card slot 4 will be set high by externalmicroprocessor 38 and the NMI port 61 would be set to signal theapplication processor 12 of a change in status. The applicationprocessor 12 is directed to card slot 4 by reading bit 7 of card slot 4which indicates that a change in status of card slot 4 is the reason thecurrent NMI interruption was sent.

While the present invention bas been described in connection with itsuse in a microcomputer using a DOS based application processor, it is tobe understood that the present invention can be utilized with a varietyof application processors in many different situations requiringexpanded and/or extended memory. It will be apparent to those skilled inthe art that various changes and enhancements of the disclosedembodiment can be made to accommodate particular situations in a givenapplication without departing from the spirit and scope of the presentinvention.

We claim:
 1. A method of interfacing an application processor with aplurality of peripheral ports, comprising the steps of:monitoring theplurality of peripheral ports with an external processor; communicatinga status change in at least one of the plurality of peripheral ports tothe application processor; evaluating the status change with theapplication processor; executing a response with the applicationprocessor in response to the status change; and communicating the statuschange evaluation and execution from the application processor to theexternal processor.
 2. The method of claim 1, wherein the step ofcommunicating a status change further comprises the step of writing abit change to a register in the at least one of the plurality ofperipheral ports.
 3. The method of claim 1, wherein the step ofevaluating the status change with the application processor furthercomprises the step of reading a plurality of bits in the at least one ofthe plurality of peripheral ports.
 4. A method of interfacing anapplication processor with a plurality of peripheral ports, comprisingthe steps of:monitoring the status of a plurality of peripheral portswith a processing element other than said application processor;communicating that status change has occurred in at least one of theplurality of peripheral ports; said application processor responding tothe status change; and updating an indicator of the changed status ofsaid at least one of the peripheral ports in said processing element. 5.The method of claim 4, wherein said processing element is a processorother than said application processor.
 6. The method of claim 4, whereinthe step of communicating a status change further comprises the step ofwriting a bit change to a register in at least one of said plurality ofperipheral ports.
 7. A method of interfacing an application processorwith a plurality of peripheral ports, comprising the steps of:monitoringthe status of a plurality of peripheral ports with a processing elementother than said application processor; communicating to said applicationprocessor that a status change has occurred in at least one of theplurality of peripheral ports; and said application processor respondingto the status change.
 8. The method of claim 7, wherein the step ofcommunicating a status change further comprises the step of writing abit change to a register in at least one of said plurality of peripheralports.
 9. The method of claim 7, wherein said processing element is aprocessor other than said application processor.
 10. The method of claim.[.7.]. .Iadd.20.Iaddend., wherein said status of at least one of saidcard slots changes when a card is inserted into at least one of saidcard slots.
 11. The method of claim .[.7.]. .Iadd.20.Iaddend., whereinsaid status of at least one of said card slots chances when a card isremoved from at least one of said card slots.
 12. The method of claim.[.7.]. .Iadd.20.Iaddend., wherein said status of at least one of saidcard slots changes when a card is inserted into at least one of saidcard slots and again changes when a card is removed from at least one ofsaid card slots.
 13. The method of claim .[.7.]. .Iadd.20.Iaddend.,wherein said application processor's response to the change in thestatus of at least one of said card slots is dynamic.
 14. A method ofinterfacing an application processor with a plurality of card slots in acomputing device, comprising the steps of:monitoring said card slots ina computing device with a processing element other than said applicationprocessor; communicating to said application processor that a change inthe status of at least one of said card slots has occurred; and saidapplication processor responding to the change in the status of at leastone of said card slots.
 15. The method of claim 14, wherein saidprocessing element is a processor other than said application processor.16. The method of claim 14, wherein said status of at least one of saidcard slots changes when a card is inserted into at least one of saidcard slots.
 17. The method of claim 14, wherein said status of at leastone of said card slots changes when a card is removed from at least oneof said card slots.
 18. The method of claim 14, wherein said status ofat least one of said card slots changes when a card is inserted into atleast one of said card slots and again changes when a card is removedfrom at least one of said card slots.
 19. The method of claim 14,wherein said application processor's response to the change in thestatus of at least one of said card slots is dynamic. .Iadd.
 20. Themethod of claim 7, wherein at least some of said peripheral ports arecard slots. .Iaddend.